IBIS Macromodel Task Group

Meeting date: 13 February 2018

Members (asterisk for those attending):
ANSYS:                        Dan Dvorscak
                            * Curtis Clark
Broadcom (Avago):             Xingdong Dai
                              Bob Miller
Cadence Design Systems:       Ambrish Varma
                              Brad Brim
                              Kumar Keshavan
                              Ken Willis
eASIC:                        David Banas
                              Marc Kowalski
Ericsson:                     Anders Ekholm
GlobalFoundries:              Steve Parker
IBM                           Luis Armenta
                              Trevor Timpane
Intel:                      * Michael Mirmak
Keysight Technologies:        Fangyi Rao
                            * Radek Biernacki
                              Ming Yan
Maxim Integrated Products:    Hassan Rafat
Mentor, A Siemens Business:   John Angulo
                            * Arpad Muranyi
Micron Technology:          * Randy Wolff
                            * Justin Butterfield
SiSoft:                     * Walter Katz
                              Todd Westerhoff
                            * Mike LaBonte
SPISim:                     * Wei-hsing Huang
Synopsys:                     Rita Horner
                              Kevin Li
Teraspeed Consulting Group:   Scott McMorrow
Teraspeed Labs:             * Bob Ross
TI:                           Alfred Chong
    
The meeting was led by Arpad Muranyi.  Curtis Clark took the minutes.

--------------------------------------------------------------------------------
Opens:

- None.

-------------
Review of ARs:

- Arpad to send BIRD189.5_draft16_v4 to the Interconnect and ATM lists.
  - Done.
  
- Bob to propose language to address his concerns about fallback to legacy
  package models with BIRD189.
  - In progress.
  
--------------------------
Call for patent disclosure:

- None.

-------------------------
Review of Meeting Minutes:

- Arpad: Does anyone have any comments or corrections? [none]
- Walter: Motion to approve the minutes.
- Michael M.: Second.
- Arpad: Anyone opposed? [none]

-------------
New Discussion:

BIRD189.5_draft17_v1
- Discussion: Arpad introduced an example/question that had been discussed
  during public and private Interconnect Group email exchanges.  Arpad noted
  that he thought a single Interconnect Model could not span two different
  regions for different pins (e.g. pin-to-pad for some pins and pin-to-buffer
  for others).  He noted that Randy had raised some examples that suggested
  that this restriction could be an inconvenience to him.  He asked Randy if
  he could elaborate.  Randy described an example in which he had a full
  package model for I/O and power pins, but did not have a detailed on-die
  power delivery or I/O interconnect model.  The on-die model consisted only of
  decoupling caps as the PDN.  His concern was whether the only way to handle
  this example with the BIRD189 syntax was to create two models.  One goes from
  pin to pad and contains the full package model.  The second model is necessary
  to create the pad to buffer model for the PDN, and the inconvenience would be
  the need to add a bunch of low-impedance paths to connect all the I/O pins
  just so the PDN could be provided.  Walter noted that two models would be
  necessary, but the on-die model need only contain the PDN and did not have to
  include low-impedance paths for all the I/O pins.  Walter noted the following
  line on page 10 of draft17_v1:
      If an *_I/O pin_name appears only in a pin to die pad Interconnect Model
      in the Interconnect Model Group, then the *_I/O pin_name electrical path
      from the die pad to buffer shall be shorted.
  Walter noted that this statement applies to any and all individual pins in the
  model, so in Randy's example the I/O pins would be automatically shorted from
  pad to buffer by the EDA tool.  Randy agreed that this was an acceptable
  solution for his example.
  
- Discussion: The group began reviewing and attempting to resolve the
  outstanding comment fields in the current draft.  Arpad started with this
  sentence, which precedes his Figure XX2 illustrating the ambiguity of a pin
  occurring multiple times as Aggressor_Only but never as a victim:
      However, the rules defined in the Usage Rules section of the [Interconnect
      Model Group] keyword above instruct the EDA vendor to select the first
      model (marked as green) for the simulation of pin 4 in this case.
  Arpad noted that the Rule to which the sentence referred had been deleted.
  Walter noted that such a model should be considered incomplete, and we need
  not worry about specifying how EDA tools deal with incomplete models.  The
  group agreed that we need only remove this sentence, as the previous sentence
  already pointed out the ambiguity.
  
  During the review, Mike L. and Randy noticed that we were reviewing topics
  that had already been addressed.  Mike L. then realized that Michael M. had
  sent out a draft17_v2, but he had only sent it to Mike L.  Arpad and Mike L.
  took the AR to fold any changes discussed in the meeting into draft17_v2 to
  create draft17_v3.

- Mike L.: Motion to adjourn.
- Curtis: Second.
- Arpad: Thank you all for joining.

AR: Arpad and Mike L. to fold changes discussed during the meeting into
    draft17_v2 to create draft17_v3.

-------------
Next meeting: 20 February 2018 12:00pm PT
-------------

IBIS Interconnect SPICE Wish List:

1) Simulator directives